Abstract—We propose a design of a 16-bit RISC CPU core using an adiabatic logic which is called a two phase drive adiabatic dynamic CMOS logic (2PADCL), in this paper. The proposed adiabatic RISC CPU is non-pipelined with a latency of three cycles, and also consists of six blocks; an arithmetic and logic unit (ALU), a program counter, a register file, an instruction decoder unit, a multiplexer and a clock control unit. Through the SPICE simulation, the 2PADCL CPU was evaluated for 0.35mm standard CMOS library and was compared with the CMOS CPU. The simulation results show that the power consumption of the adiabatic CPU is about 1/4 compared to that of the CMOS CPU.

Index Terms—Adiabatic logic, RISC, CPU, non-pipelined.

Yasuhiro Takahashi is with the Department of Electrical and Electronic,Gifu University, Gifu-shi, 501-1193, Japan, (email: yasut@gifu-u.ac.jp).
Toshikazu Sekine is with the Department of Electrical and Electronic,Gifu University, Gifu-shi, 501-1103, Japan, (email: sekine@gifu-u.ac.jp).
Michio Yokoyama is with the Department of Bio-system Engineering,Yamagata University, Yonezawa-shi, 992-8510, Japan, (email:yoko@yz.yamagata-u.ac.jp).

Cite: Yasuhiro Takahashi, Toshikazu Sekine,and Michio Yokoyama, "Design of a 16-bit Non-pipelined RISC CPU in a Two Phase Drive Adiabatic Dynamic  CMOS  Logic,"  International  Journal  of  Computer  and  Electrical Engineering, vol. 1, no. 1, pp. 71-76, 2009.