Abstract—Multiplication is an important fundamental operation in most signal and image processing applications. High definition image processing has put a huge demand on fast and massive data processing and shrinking the CMOS process made the silicon real estate available to provide for such massive data processing building blocks. We compare large width multipliers from an architecture point of view, maximum clock frequency, latency, throughput, resource usage, power consumption. We use a flopped combinational baseline multiplier for our comparison and we use the same FPGA platform to be fair in our analysis. We mention some remarks and conclude that shift and add is the best.