Architecture for Isolating Defective Two Port SRAM Memories

IJCEE 2012 Vol.4(6): 958-961 ISSN: 1793-8163 DOI: 10.7763/IJCEE.2012.V4.645

A. Padma Sravani and M. Satyam

Abstract—This paper presents a method of implementing fault isolation for word-oriented SRAM memories. It uses Built in Self Test (BIST) technique to locate the faults. Isolation circuit is used to isolate the faults by using switches. The detection and isolation of faulty rows is done at power on. Based on defect injection in SPICE simulation, faults are generated and tested.

Index Terms—Fault isolation, BIST, process variations, Two-port SRAM memory.

Padma Sravani Annam is with IIIT Hyderabad, India (email: padmasravani.a@research.iiit.ac.in)

Cite: A. Padma Sravani and M. Satyam, "Architecture for Isolating Defective Two Port SRAM Memories,"International Journal of Computer and Electrical Engineering vol. 4, no. 6, pp. 958-961, 2012.

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General Information

ISSN: 1793-8163 (Print)

Abbreviated Title: Int. J. Comput. Electr. Eng.

Frequency: Quarterly

DOI: 10.17706/IJCEE

Editor-in-Chief: Prof. Yucong Duan

Abstracting/ Indexing: INSPEC, Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library

E-mail: ijcee@iap.org

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