Abstract—This paper discusses about the implementation of a low power design technique, clock gating, on Direct Memory Access (DMA) at Register Transfer Level (RTL). Modification has been done to the existing clock gating circuitry by adding and utilizing the reset signal of a register as an additional enable pin. The modification approach and the method to identify appropriate clock gating candidates have been discussed. The power consumptions and few other factors including speed and area were estimated. The results were compared with two different methods of clock gating implementations, fine-grain clock gating and global clock gating. A total of 38% of dynamic power reduction has been achieved when both, global clock gating and fine-grain clock gating were implemented simultaneously.

Index Terms—Clock gating, dynamic power,leakage power,and low power VLSI design.

Shabagran Gandi and Zulfiqar Ali are with the School of Electrical and Electronics Engineering, Universiti Sains Malaysia, Penang, Malaysia(e-mail: shabagran.a.gandi@intel.com, eezulfiq@eng.usm.my)
Suphachai Sutanthavibul is with the Intel Microelectronics, Folsom,California, and USA (e-mail: suphachai.sutanthavibul@intel.com).

Cite: Shabagran Gandi, Zulfiqar Ali, and Suphachai Sutanthavibul, "Clock Gating Implementation on Direct Memory Access," International Journal of Computer and Electrical Engineering vol. 4, no. 6, pp. 846-849, 2012.