Abstract—CMOS transistors have been consistently scaled to smaller feature sizes and continue to reduce towards sub-0.1 um lengths. However, as the channel length decreases, so does the gate oxide thickness, dictating a decrease in the supply voltage. Driven by the needs for low power, small size and low cost, CMOS radio frequency integrated circuits (RFIC) design becomes main stream in modern portable wireless communications. The ultimate goal in RFIC design is to having battery-less systems so as to decrease power dissipation. Commonly a Low Noise Amplifier (LNA) is a key component is RF front end receiver which poses a challenge in terms of meeting high gain, low noise figure, good linearity and low power consumption requirement. The primary role of the LNA is to lower the overall noise figure of the entire RF front end, noise optimization is considered as one of the most critical steps in the LNA design procedure. A 0.7V, 1GHz low noise amplifier has been designed and simulated using spectre simulator in a standard TCMC 0.18um CMOS technology. With low power noise optimization techniques, the amplifier provides the gain of 23dB, a noise figure of only 1.1dB, power dissipation of 8.4mw from 0.7v power supply.

Index Terms—Low Noise Amplifier (LNA), Noise Figure (N.F), Radio Frequency (RF) and CMOS.

Zamin Ali Khan is a foreign faculty member at Department of Computer Science, University of Karachi. He is also supervising VLSI Research Lab.Email:zaminkhan@uok.edu.pk.
S. M. Aqil. Burney is the Professor and the Chairman at Department of Computer Science, University of Karachi. He is also the director of UBIT.Email:burney@uok.edu.pk.

[PDF]

Cite: M. Zamin Ali Khan and S. M. Aqil Burney, "Statistical Approach to Design Low Noise Amplifier," International Journal of Computer and Electrical Engineering vol. 3, no. 4, pp. 606-610, 2011.