Abstract—Recent research has proposed several low-power design techniques for VLSI circuitry in nano-scale CMOS era. However, these techniques always involve custom layout design or novel Electronic Design Automation (EDA) flows. In this paper essential low power techniques such as voltage separation, body bias and power switch are implemented in existent place and route (P&R) tools. These techniques enable the possibility to integrated low power techniques into standard Cell-Based physical design flow. The result of these research shows a little overhead in design procedure equally area overhead compare with fully custom design flow. The proposed low power design techniques can be cooperated with modern power management system to enable the power reduction in targeting circuitry with small implementation overheads.

Index Terms—Cell-Based, Low-power, Nano-scale, physical design, Place and route.

A.R.Aswath is with the Department of Electronics & Communication,DayanandaSagar College of Engineering, Kumaraswamy Layout Bangalore-560078 , Karnataka, India (email:aswath.ar@gmail.com.)
M.Puttaraju is with the Department of Medical Electronics,DayanandaSagar College of Engineering, Kumaraswamy Layout Bangalore-560078 , Karnataka, India (email:Puttaraju_ml@hotmail.com)A.B.Kalpana is with the Department of Electronics and Communication,Bangalore Institute of technology, Bangalore-560004, Karnataka, India(email:abkalpana@gmail.com).

Cite: A. R. Aswath, M. Puttaraju, and A. B. Kalpana, "An Implementation of Integral Low Power Techniques for Modern Cell-Based VLSI Designs," International Journal of Computer and Electrical Engineering vol. 3, no. 3, pp. 394-397, 2011.