Abstract—Along with sharply increasing bandwidth requirements, modern network applications and new protocols demand highly intelligent and sophisticated processing over the network. Since these workloads require processing capability beyond state-of-the-art microprocessors, parallel architectures are required in order to handle the packet data without slowing down line speed. Network processors with various parallel architectures are appearing in the market, however, a thorough investigation of the implications of static versus dynamic scheduling of this class of emerging workloads has not been done. In this paper, we characterize the performance and power dissipation of statically identified ILP architectures, and we also compare them to dynamically scheduled architectures for network processing. In dynamically scheduled architectures, the power consumption of the instruction window greatly increases with increasing issue widths. On the other hand, statically scheduled architectures show better performance, as well as tremendous advantages in power, since they do not have instruction window wakeup/select, reorder buffer, and other scheduling related hardware modules. With the large parallelism and the loop nature of network applications, our experimental analysis supports static scheduling as an appropriate strategy for network processor applications.

Index Terms—Network processors, ILP, performance evaluation, workload characterization.

B. Lee, is with the Department of Electrical and Computer Engineering,The University of Texas at San Antonio, San Antonio, Texas 78249 USA.Phone: +1 210 4585027; Fax: +1 210 4585947; e-mail:byeong.lee@utsa.edu.

Cite: Byeong Kil Lee, "Exploiting Statically Identified ILP for Network Processor Applications," International
Journal of Computer and Electrical Engineering vol. 2, no. 5, pp. 830-837, 2010.