Abstract—Pulse Width Modulation (PWM) is a common technique used in many different applications. This technique is the heart of the inverter system. This paper reported a modified strategy in asynchronous unipolar sinusoidal PWM (SPWM) switching scheme based on ACEX1K50TC144-3 Altera Field Programmable Gate Array (FPGA). The carrier frequency was designed for 20 kHz and the fundamental frequency was designed to adjust 1 to 100 Hz, with step increase in 1 Hz. A new SPWM signal generation strategy is proposed and compared to traditional SPWM generation technique. The design entry is conducted by Max+plus II version 10.2 through schematic and VHDL programming. The verification in level simulation and hardware realization has been done. As the result, the proposed modified SPWM signal generation strategy works properly and can reduces the usage of logic cell (LC) until 63.75%.

Index Terms—Drive, FPGA, inverter, PWM.

Tole Sutikno is with the Department of Electrical Engineering, Faculty of Industrial Technology, Universitas Ahmad Dahlan (UAD), Yogyakarta, Indonesia e-mail: thsutikno@ieee.org or tole@ee.uad.ac.id
Mochammad Facta is with the Department of Electrical Engineering, Faculty of Engineering, Universitas Diponegoro (UNDIP), Semarang, Indonesia, e-mail: facta@ieee.org or facta@elektro.ft.undip.ac.id

Cite: Tole Sutikno and Mochammad Facta, "An Efficient Strategy to Generate High Resolution Three-Phase Pulse Width Modulation Signal Based on Field Programmable  Gate  Array,"  International  Journal  of  Computer  and
Electrical Engineering vol. 2, no. 3, pp. 413-416, 2010.